1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, a semiconductor device, and a semiconductor device fabrication method and, more particularly, to technology for reducing the leak current of the semiconductor integrated circuit.
2. Description of Related Art
In recent years, the demand for increased intricacy in semiconductor integrated circuits has grown steadily. A reduction in the voltages of power sources has accompanied this increase in the intricacy of semiconductor integrated circuits. In order to lower the supply voltage, the threshold value voltage of the transistor constituting the semiconductor integrated circuit must be set low. For example, when the supply voltage is 1 volt, the threshold value voltage of a field effect transistor is desirably on the order of 0.2 to 0.3 volt. However, the lower the threshold value voltage, the greater the leak current when the field effect transistor is turned OFF. For this reason, when the threshold value voltage is lowered, the power consumption when the semiconductor integrated circuit is not operating increases.
Circuits such as the one shown in FIG. 6, for example, are known as semiconductor integrated circuits that resolve these drawbacks. In the circuit in FIG. 6, a pMOS transistor 610 and an nMOS transistor 620 constitute an inverter. Further, an nMOS transistor 630 used to prevent a leak current is provided between the nMOS transistor 620 and the ground line. An operation control signal is input to the gate of the nMOS transistor 630. In accordance with this operation control signal, the nMOS transistor 630 is always ON when the semiconductor integrated circuit is in an operational state, and always OFF when same is not operating. An enhancement mode MOS transistor with a low threshold value voltage is used as the pMOS transistor 610 and the nMOS transistor 620. On the other hand, the nMOS transistor 630 is a high threshold value enhancement mode MOS transistor, and hence the leak current in an OFF state is extremely small. Thus, because the nMOS transistor 630 is used, the power consumption when the semiconductor integrated circuit is not operating is reduced.
As a technology for reducing the leak current, the semiconductor integrated circuit appearing in the Japanese Patent Application Laid Open No. 05-268027 below, for example, is also known. With this circuit, a reduction of the leak current is achieved by raising the back gate bias of the nMOS transistor when the current penetrating same has increased.
In addition, technologies for forming semiconductor devices by using an SOI (Silicon On Insulator) substrate are known from the prior art. By using an SOI substrate, it is easy to increase the intricacy and speed of the semiconductor integrated circuit. Known semiconductor devices which employ an SOI substrate are those appearing in Japanese Patent Application Laid Open No. 06-013606 and U.S. Pat. No. 6,043,536, for example.
In the semiconductor integrated circuit shown in FIG. 6, an operation control signal is input from the outside, and hence a signal terminal fulfilling this purpose is required. Consequently, there is the drawback that the surface area of the wiring layer increases.
Further, in the case of this semiconductor integrated circuit, the threshold value voltage of the nMOS transistor 630 is raised by increasing the impurity concentration of the SOI layer. Hence, there is the drawback that the withstand voltage of the nMOS transistor 630 then drops due to the parasitic bipolar effect.
On the other hand, the semiconductor integrated circuit disclosed in Japanese Patent Application Laid Open No. 05-268027 must be a circuit for controlling the back gate bias by detecting an increase in the penetration current, and there is therefore the drawback that the circuit scale is then extremely large.